• 1st Hardware - a few lots from single tools at each operation only.
• Early Design / Test / Process window issues > lower yields.
• Process vs. product maturity > many signatures for analysis.
• Product debug, design characterization and customer samples.
• Generate Qualification lots - excursion vs. baseline issue risks.
  
  

• Good data correlation capability, covering CP, Device, Defect & Inline data for analysis within the same data types & across multiple data types.
  
• Single and Composite map analysis for data types; CP, Device, Defect and In-line.
  
• Map overlay between certain data types: CP overlay with Device or Defect.
  
• Statistical analysis for correlation studies and testing different sample groups.
  
• Lot characterization reports / charts for local analysis & reporting to remote development resources.
  
• Die / Panel level classification for the 1st Yield Loss and defect impact calculations.
  
• Fab 'Run card' information.
• Parametric and Defect Code reports.
  
• Wafer / Glass level failure pareto charts (Bin, Test, vector, Defect Code, ...).
  
• Wafer / Glass & Lot level Yield reports
  

Characterisation of 1st Hardware.

• Higher Fab volume.  Design, process, product and test maturing.
• Second, third,... equipment releases at the same process steps.
• Improving yields, but high variability on both old & new hardware.
• Characterization is complete.  1st design/process fixes underway.
• Many loss signatures and classification/prioritisation is required.
• "Systematic Defects"- 1st core technology issues understood.
  
• 1st Yield Improvement Roadmap (YIR) defined.
  
  

• Equipment Correlation trends.
  
• Timeline commonality analysis.
• Equipment/Recipe/Operator commonality.
  
• Advanced commonality tools.
  
• Design and Analysis of Experiments.
  
• Temporary process change analysis.
  
• Process grade monitoring.
  
• Wafer / Glass level classification.
  
• Yield limiter Analysis.
• Yield loss pareto generation.
  
• Yield roadmap and yield model definitions.
  
• "Collections", Knowledge Management.
  
• Track process changes, contain events.
  
• Yield prediction functionality.
  
• Implement 1st personal Data Analysis preferences & job scheduling systems.
• Establish cross functional Yield Improvement teams and Steering Groups.
• Standardise routine activities into documented workflow systems.
• Documentation of signatures and associated Engineering reports (KM).

Drive 1st opportunities through detect, fix, pilot verification and successful closure.

• Main volume ramp complete.  Yield Roadmap 90% of tasks done.
• Fewer issues, focus on sustaining and excursion control.
• "Random Defects" - continuous drive for reduced defectivity.
  
• Continuous Improvement emphasis is on finding remaining yield opportunities, process simplification and cost reduction.
  
• Reduce variation and "Tighten the distribution".
• Fewer resources supporting higher volume.
  
  

• Phase I & 2 Engineering Data Analysis tools but with added automation.
  
• 'Point & Click' Lot review and classification.
  
• Change from Wafer / Glass based classification to Lot level classification.
• Automated lot review (pattern recognition), excursion detection and 1st pass debug.
  
• Batch systems for Lot and Time based Engineering Data Analysis.
  
• Full implementation of Knowledge Management and Systematic workflows. (preferably with MES interfaces).
  
• Parametric Sensitivity Analysis.
• Defect Kill ratio analysis.
• Higher Volume pilot analysis "Shotgun" correlation.
  
• Background Commonality studies.
• Principal Component analysis, Decision Trees and Data mining.
  
• Process Window analysis & fine tuning.
• Best Tool matching.
  
• HILO yield analysis.
  

Continuous Improvement becomes part of the Company culture.